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k30p81m72sf1 k30 sub-family supports: mk30dx64vlk7, mk30dx128vlk7, mk30dx256vlk7, mk30dx64vmb7, MK30DX128VMB7, mk30dx256vmb7 features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 105c ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C 10 low-power modes to provide power optimization based on application requirements C 16-channel dma controller, supporting up to 63 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C 128-bit unique identification (id) number per chip ? human-machine interface C segment lcd controller supporting up to 36 frontplanes and 8 backplanes, or 40 frontplanes and 4 backplanes, depending on the package size C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C two 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C 12-bit dac C three analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C eight-channel motor control/general purpose/pwm timer C two 2-channel quadrature decoder/general purpose timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C controller area network (can) module C two spi modules C two i2c modules C four uart modules C i2s module freescale semiconductor document number: k30p81m72sf1 data sheet: technical data rev. 2, 4/2012 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2012 freescale semiconductor, inc.
table of contents 1 ordering parts ........................................................................... 3 1.1 determining valid orderable parts...................................... 3 2 part identification ...................................................................... 3 2.1 description......................................................................... 3 2.2 format ............................................................................... 3 2.3 fields ................................................................................. 3 2.4 example ............................................................................ 4 3 terminology and guidelines ...................................................... 4 3.1 definition: operating requirement...................................... 4 3.2 definition: operating behavior ........................................... 5 3.3 definition: attribute ............................................................ 5 3.4 definition: rating ............................................................... 6 3.5 result of exceeding a rating .............................................. 6 3.6 relationship between ratings and operating requirements...................................................................... 6 3.7 guidelines for ratings and operating requirements............ 7 3.8 definition: typical value..................................................... 7 3.9 typical value conditions .................................................... 8 4 ratings ...................................................................................... 9 4.1 thermal handling ratings ................................................... 9 4.2 moisture handling ratings .................................................. 9 4.3 esd handling ratings ......................................................... 9 4.4 voltage and current operating ratings ............................... 9 5 general ..................................................................................... 10 5.1 ac electrical characteristics .............................................. 10 5.2 nonswitching electrical specifications ............................... 10 5.2.1 voltage and current operating requirements ......... 10 5.2.2 lvd and por operating requirements ................. 12 5.2.3 voltage and current operating behaviors .............. 12 5.2.4 power mode transition operating behaviors .......... 13 5.2.5 power consumption operating behaviors .............. 14 5.2.6 designing with radiated emissions in mind ........... 18 5.2.7 capacitance attributes .......................................... 18 5.3 switching specifications..................................................... 19 5.3.1 device clock specifications ................................... 19 5.3.2 general switching specifications ........................... 19 5.4 thermal specifications ....................................................... 20 5.4.1 thermal operating requirements ........................... 20 5.4.2 thermal attributes ................................................. 21 6 peripheral operating requirements and behaviors .................... 22 6.1 core modules .................................................................... 22 6.1.1 debug trace timing specifications ......................... 22 6.1.2 jtag electricals .................................................... 23 6.2 system modules ................................................................ 25 6.3 clock modules ................................................................... 25 6.3.1 mcg specifications ............................................... 25 6.3.2 oscillator electrical specifications ......................... 28 6.3.3 32khz oscillator electrical characteristics............ 30 6.4 memories and memory interfaces ..................................... 31 6.4.1 flash electrical specifications................................ 31 6.4.2 ezport switching specifications ............................ 35 6.5 security and integrity modules .......................................... 36 6.6 analog ............................................................................... 36 6.6.1 adc electrical specifications ................................. 37 6.6.2 cmp and 6-bit dac electrical specifications ......... 45 6.6.3 12-bit dac electrical characteristics ..................... 47 6.6.4 voltage reference electrical specifications ............ 50 6.7 timers................................................................................ 51 6.8 communication interfaces ................................................. 52 6.8.1 can switching specifications ................................ 52 6.8.2 dspi switching specifications (limited voltage range) .................................................................... 52 6.8.3 dspi switching specifications (full voltage range). 53 6.8.4 i2c switching specifications .................................. 55 6.8.5 uart switching specifications .............................. 55 6.8.6 i2s/sai switching specifications .......................... 55 6.9 human-machine interfaces (hmi)...................................... 60 6.9.1 tsi electrical specifications ................................... 60 6.9.2 lcd electrical characteristics ................................ 61 7 dimensions ............................................................................... 62 7.1 obtaining package dimensions ......................................... 62 8 pinout ........................................................................................ 63 8.1 k30 signal multiplexing and pin assignments .................. 63 8.2 k30 pinouts ....................................................................... 68 9 revision history ........................................................................ 70 k30 sub-family data sheet, rev. 2, 4/2012. 2 freescale semiconductor, inc.
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers: pk30 and mk30 . 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status m = fully qualified, general market flow p = prequalification k## kinetis family k30 a key attribute d = cortex-m4 w/ dsp f = cortex-m4 w/ dsp and fpu m flash memory type n = program flash only x = program flash and flexmemory table continues on the next page... rdering parts sub-family data sheet, rev. , /. freescale semiconductor, inc.
field description values fff program flash memory size 32 = 32 kb 64 = 64 kb 128 = 128 kb 256 = 256 kb 512 = 512 kb 1m0 = 1 mb r silicon revision z = initial (blank) = main a = revision after main t temperature range (c) v = ?40 to 105 c = ?40 to 85 pp package identifier fm = 32 qfn (5 mm x 5 mm) ft = 48 qfn (7 mm x 7 mm) lf = 48 lqfp (7 mm x 7 mm) lh = 64 lqfp (10 mm x 10 mm) mp = 64 mapbga (5 mm x 5 mm) lk = 80 lqfp (12 mm x 12 mm) mb = 81 mapbga (8 mm x 8 mm) ll = 100 lqfp (14 mm x 14 mm) ml = 104 mapbga (8 mm x 8 mm) mc = 121 mapbga (8 mm x 8 mm) lq = 144 lqfp (20 mm x 20 mm) md = 144 mapbga (13 mm x 13 mm) mj = 256 mapbga (17 mm x 17 mm) cc maximum cpu frequency (mhz) 5 = 50 mhz 7 = 72 mhz 10 = 100 mhz 12 = 120 mhz 15 = 150 mhz n packaging type r = tape and reel (blank) = trays 2.4 example this is an example part number: mk30dn512zvmd10 3 terminology and guidelines terminology and guidelines k30 sub-family data sheet, rev. 2, 4/2012. 4 freescale semiconductor, inc.
3.1 definition: operating requirement an operating requirement is a speciied value or range o values or a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useul lie o the chip ample his is an eample o an operating requirement hich you must meet or the accompanying operating behaviors to be guaranteed ymbol escription in a nit core supply voltage einition operating behavior n operating behavior is a speciied value or range o values or a technical characteristic that are guaranteed during operation i you meet the operating requirements and any other speciied conditions ample his is an eample o an operating behavior hich is guaranteed i you meet the accompanying operating requirements ymbol escription in a nit igital o ea pullup pulldon current einition ttribute n attribute is a speciied value or range o values or a technical characteristic that are guaranteed regardless o hether you meet the operating requirements erminology and guidelines ubamily ata heet ev reescale emiconductor nc
3.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 3.4 definition: rating a rating is a minimum or maimum value o a technical characteristic that i eceeded may cause permanent chip ailure operating ratings apply during operation o the chip handling ratings apply hen the chip is not poered ample his is an eample o an operating rating ymbol escription in a nit core supply voltage esult o eceeding a rating easured characteristic operating rating ailures in time ppm he lielihood o permanent chip ailure increases rapidly as soon as a characteristic begins to eceed one o its operating ratings erminology and guidelines ubamily ata heet ev reescale emiconductor nc
3.6 relationship between ratings and operating requirements ? typical value is a speciied value or a technical characteristic that ies ithin the range o values speciied by the operating behavior iven the typical manuacturing process is representative o that characteristic during operation hen you meet the typicalvalue conditions or other speciied conditions ypical values are provided as design guidelines and are neither tested nor guaranteed erminology and guidelines ubamily ata heet ev reescale emiconductor nc
3.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 3.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c ?40 c v dd (v) i (?a) dd_stop t j 3.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v terminology and guidelines k30 sub-family data sheet, rev. 2, 4/2012. 8 freescale semiconductor, inc.
4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature ?55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . . determined according to ic/jedec standard j-std-, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . . moisture handling ratings symbol description min. max. nit notes msl moisture sensitivity level . determined according to ic/jedec standard j-std-, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . . esd handling ratings symbol description min. max. nit notes hbm electrostatic discharge voltage, human body model - cdm electrostatic discharge voltage, charged-device model - i lat latch-up current at ambient temperature of c - ma . determined according to jedec standard jesd-a, electrostatic discharge (esd) sensitivity testing human body model (hbm) . . determined according to jedec standard jesd-c, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . oltage and current operating ratings symbol description min. max. nit dd digital supply voltage . . table continues on the next page... ratings sub-family data sheet, rev. , /. freescale semiconductor, inc.
symbol description min. max. unit i dd digital supply current 185 ma v dio digital input voltage (except reset, extal, and xtal) ?0.3 5.5 v v aio analog 1 , reset, extal, and xtal input voltage ?0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all port pins) ?25 25 ma v dda analog supply voltage v dd ? 0.3 v dd + 0.3 v v bat rtc battery supply voltage ?0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 5.2 nonswitching electrical specifications general k30 sub-family data sheet, rev. 2, 4/2012. 10 freescale semiconductor, inc.
5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd ? v dda v dd -to-v dda differential voltage ?0.1 0.1 v v ss ? v ssa v ss -to-v ssa differential voltage ?0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage 2.7 v ? v dd ? 3.6 v 1.7 v ? v dd ? 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icdio digital pin negative dc injection current single pin v in < v ss -0.3v -5 ma 1 i icaio analog 2 , extal, and xtal pin dc injection current single pin v in < v ss -0.3v (negative current injection) v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins negative current injection positive current injection -25 +25 ma v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v dio_min (=v ss -0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i ic |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is greater than v aio_min (=v ss -0.3v) and v in is less than v aio_max (=v dd +0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if these limits cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i ic |. the positive injection current limiting resistor is calcualted as r=(v in -v aio_max )/|i ic |. select the larger of these two calculated resistances. general k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 11
5.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range level 1 falling (lvwv=00) level 2 falling (lvwv=01) level 3 falling (lvwv=10) level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 ?s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v general k30 sub-family data sheet, rev. 2, 4/2012. 12 freescale semiconductor, inc.
5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage high drive strength 2.7 v ? v dd ? 3.6 v, i oh = -9ma 1.71 v ? v dd ? 2.7 v, i oh = -3ma v dd ? 0.5 v dd ? 0.5 v v output high voltage low drive strength 2.7 v ? v dd ? 3.6 v, i oh = -2ma 1.71 v ? v dd ? 2.7 v, i oh = -0.6ma v dd ? 0.5 v dd ? 0.5 v v i oht output high current total for all ports 100 ma v ol output low voltage high drive strength 2.7 v ? v dd ? 3.6 v, i ol = 9ma 1.71 v ? v dd ? 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength 2.7 v ? v dd ? 3.6 v, i ol = 2ma 1.71 v ? v dd ? 2.7 v, i ol = 0.6ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 ?a 1 i in input leakage current (per pin) at 25c 0.025 ?a 1 i oz hi-z (off-state) leakage current (per pin) 1 ?a r pu internal pullup resistors 20 50 k? 2 r pd internal pulldown resistors 20 50 k? 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss 3. measured at v dd supply voltage = v dd min and vinput = v dd 5.2.4 power mode transition operating behaviors all specifications except t por , and vllsx
table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 ?s 1 vlls1 table continues on the next page... eneral sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.46 ma 7 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.61 ma 8 i dd_stop stop mode current at 3.0 v @ ?40 to 25c @ 70c @ 105c 0.35 0.384 0.628 0.567 0.793 1.2 ma ma ma i dd_vlps very-low-power stop mode current at 3.0 v @ ?40 to 25c @ 70c @ 105c 5.9 26.1 98.1 32.7 59.8 188 ?a ?a ?a i dd_lls low leakage stop mode current at 3.0 v @ ?40 to 25c @ 70c @ 105c 2.6 10.3 42.5 8.6 29.1 92.5 ?a ?a ?a 9 i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v @ ?40 to 25c @ 70c @ 105c 1.9 6.9 28.1 5.8 12.1 41.9 ?a ?a ?a 9 i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v @ ?40 to 25c @ 70c @ 105c 1.59 4.3 17.5 5.5 9.5 34 ?a ?a ?a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v @ ?40 to 25c @ 70c @ 105c 1.47 2.97 12.41 5.4 8.1 32 ?a ?a ?a i dd_vbat average current with rtc and 32khz disabled at 3.0 v @ ?40 to 25c @ 70c @ 105c 0.19 0.49 2.2 0.22 0.64 3.2 ?a ?a ?a table continues on the next page... eneral sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vbat average current when cpu is not accessing rtc registers @ 1.8v @ ?40 to 25c @ 70c @ 105c @ 3.0v @ ?40 to 25c @ 70c @ 105c 0.57 0.90 2.4 0.67 1.0 2.7 0.67 1.2 3.5 0.94 1.4 3.9 ?a ?a ?a ?a ?a ?a 10 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. 72mhz core and system clock, 36mhz bus clock, and 24mhz flash clock. mcg configured for fee mode. all peripheral clocks disabled. 3. 72mhz core and system clock, 36mhz bus clock, and 24mhz flash clock. mcg configured for fee mode. all peripheral clocks enabled. 4. max values are measured with cpu executing dsp instructions. 5. 25mhz core, system, bus and flash clock. mcg configured for fei mode. 6. 4 mhz core and system clock, 4 mhz and bus clock, and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 7. 4 mhz core and system clock, 4 mhz and bus clock, and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 4 mhz core and system clock, 4 mhz and bus clock, and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 9. data reflects devices with 128 kb of ram. 10. includes 32khz oscillator current and rtc operation. 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at greater than 50 mhz frequencies. ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfl general k30 sub-family data sheet, rev. 2, 4/2012. 16 freescale semiconductor, inc.
figure 2. run mode supply current vs. core frequency general k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 17
figure 3. vlpr mode supply current vs. core frequency 5.2.6 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to http://www.freescale.com . 2. perform a keyword search for emc design. 5.2.7 capacitance attributes table 7. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf table continues on the next page... eneral sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 7. capacitance attributes (continued) symbol description min. max. unit c in_d input capacitance: digital pins 7 pf 5.3 switching specifications 5.3.1 device clock specifications table 8. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 72 mhz f bus bus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f lptmr_erclk lptmr external reference clock 16 mhz f flexcan_erclk flexcan external reference clock 8 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, and i 2 c signals. general k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 19
table 9. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) slew disabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v slew enabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v 12 6 36 24 ns ns ns ns 4 port rise and fall time (low drive strength) slew disabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v slew enabled 1.71 ? v dd ? 2.7v 2.7 ? v dd ? 3.6v 12 6 36 24 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75pf load 5. 15pf load 5.4 thermal specifications general k30 sub-family data sheet, rev. 2, 4/2012. 20 freescale semiconductor, inc.
5.4.1 thermal operating requirements table 10. thermal operating requirements symbol description min. max. unit t j die junction temperature ?40 125 c t a ambient temperature ?40 105 c 5.4.2 thermal attributes board type symbol description 81 mapbga 80 lqfp unit notes single-layer (1s) r
2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horiontal. for the lf, the board meets the jesd- specification. for the maba, the board meets the jesd- specification. . determined according to jedec standard jesd-, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horiontal. for the lf, the board meets the jesd- specification. . determined according to jedec standard jesd-, integrated circuit thermal test method environmental conditionsjunction-to-board . board temperature is measured on the top surface of the board near the pacage. . determined according to method . of mil-std , test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the pacage and the cold plate. . determined according to jedec standard jesd-, integrated circuits thermal test method environmental conditionsnatural convection (still air) . eripheral operating reuirements and behaviors . core modules .. debug trace timing specifications table . debug trace operating behaviors symbol description min. max. nit t cyc cloc period freuency dependent mh t wl low pulse width ns t wh high pulse width ns t r cloc and data rise time ns t f cloc and data fall time ns t s data setup ns t h data hold ns figure . traceclt specifications eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
th ts ts th trace_clkout trace_d[3:0] figure 5. trace data specifications 6.1.2 jtag electricals table 12. jtag voltage range electricals symbol description min. max. unit operating voltage 2.7 5.5 v j1 tclk frequency of operation jtag cjtag 10 5 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width jtag cjtag 100 200 ns ns ns j4 tclk rise and fall times 1 ns j5 tms input data setup time to tclk rise jtag cjtag 53 112 ns j6 tdi input data setup time to tclk rise 8 ns j7 tms input data hold time after tclk rise jtag cjtag 3.4 3.4 ns j8 tdi input data hold time after tclk rise 3.4 ns j9 tclk low to tms data valid jtag cjtag 48 85 ns j10 tclk low to tdo data valid 48 ns j11 output data hold/invalid time after clock edge 1 3 ns 1. they are common for jtag and cjtag. input transition = 1 ns and output load = 50pf peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 23
j2 j3 j3 j4 j4 tclk (input) figure 6. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 7. boundary scan (jtag) timing peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 24 freescale semiconductor, inc.
j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 8. test access port timing j14 j13 tclk trst figure 9. trst timing 6.2 system modules there are no specifications necessary for the devices system modules. 6.3 clock modules peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 25
6.3.1 mcg specifications table 13. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 13. mcg specifications (continued) symbol description min. typ. max. unit notes f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter f vco = 48 mhz f vco = 98 mhz 180 150 ps t fll_acquire fll target frequency acquisition time 1 ms 6 pll f vco vco operating frequency 48.0 100 mhz i pll pll operating current pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) 1060 a 7 i pll pll operating current pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) 600 a 7 f pll_ref pll reference frequency range 2.0 4.0 mhz j cyc_pll pll period jitter (rms) f vco = 48 mhz f vco = 100 mhz 120 50 ps ps 8 j acc_pll pll accumulated jitter over 1s (rms) f vco = 48 mhz f vco = 100 mhz 1350 600 ps ps 8 d lock lock entry frequency tolerance 1.49 2.98 % d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 9 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation (
6. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. excludes any oscillator currents that are also consuming power while pll is in operation. 8. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 9. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 6.3.2 oscillator electrical specifications this section provides the electrical characteristics of the module. 6.3.2.1 oscillator dc electrical specifications table 14. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 500 200 300 950 1.2 1.5 na ?a ?a ?a ma ma 1 i ddosc supply current high gain mode (hgo=1) 32 khz 4 mhz 8 mhz (range=01) 16 mhz 24 mhz 32 mhz 25 400 500 2.5 3 4 ?a ?a ?a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 14. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes r f feedback resistor low-frequency, low-power mode (hgo=0) m? 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m? feedback resistor high-frequency, low-power mode (hgo=0) m? feedback resistor high-frequency, high-gain mode (hgo=1) 1 m? r s series resistor low-frequency, low-power mode (hgo=0) k? series resistor low-frequency, high-gain mode (hgo=1) 200 k? series resistor high-frequency, low-power mode (hgo=0) k? series resistor high-frequency, high-gain mode (hgo=1) 0 k? v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer?s recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.2.2 oscillator frequency specifications table 15. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode (mcg_c2[range]=00) 32 40 khz table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 15. oscillator frequency specifications (continued) symbol description min. typ. max. unit notes f osc_hi_1 oscillator crystal or resonator frequency high frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fbe to fei mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 6.3.3 32khz oscillator electrical characteristics this section describes the module electrical characteristics. 6.3.3.1 32khz oscillator dc electrical specifications table 16. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m? c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 30 freescale semiconductor, inc.
6.3.3.2 32khz oscillator frequency specifications table 17. 32khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 1. proper pc board layout procedures must be followed to achieve specifications. 6.4 memories and memory interfaces 6.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 18. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 ?s t hversscr sector erase high-voltage time 13 113 ms 1 t hversblk32k erase block high-voltage time for 32 kb 52 452 ms 1 t hversblk256k erase block high-voltage time for 256 kb 104 904 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 19. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk32k t rd1blk256k read 1s block execution time 32 kb data flash 256 kb program flash 0.5 1.7 ms ms t rd1sec1k read 1s section execution time (data flash sector) 60 ?s 1 t rd1sec2k read 1s section execution time (program flash sector) 60 ?s 1 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 19. flash command timing specifications (continued) symbol description min. typ. max. unit notes t pgmchk program check execution time 45 ?s 1 t rdrsrc read resource execution time 30 ?s 1 t pgm4 program longword execution time 65 145 ?s t ersblk32k t ersblk256k erase flash block execution time 32 kb data flash 256 kb program flash 55 122 465 985 ms ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t pgmsec512p t pgmsec512d t pgmsec1kp t pgmsec1kd program section execution time 512 b program flash 512 b data flash 1 kb program flash 1 kb data flash 2.4 4.7 4.7 9.3 ms ms ms ms t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 ?s 1 t pgmonce program once execution time 65 ?s t ersall erase all blocks execution time 175 1500 ms 2 t vfykey verify backdoor access key execution time 30 ?s 1 t swapx01 t swapx02 t swapx04 t swapx08 swap control execution time control code 0x01 control code 0x02 control code 0x04 control code 0x08 200 70 70 150 150 30 ?s ?s ?s ?s t pgmpart32k program partition for eeprom execution time 32 kb flexnvm 70 ms t setramff t setram8k t setram32k set flexram function execution time: control code 0xff 8 kb eeprom backup 32 kb eeprom backup 50 0.3 0.7 0.5 1.0 ?s ms ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 175 260 ?s 3 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 19. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr8b8k t eewr8b16k t eewr8b32k byte-write to flexram execution time: 8 kb eeprom backup 16 kb eeprom backup 32 kb eeprom backup 340 385 475 1700 1800 2000 ?s ?s ?s word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 175 260 ?s t eewr16b8k t eewr16b16k t eewr16b32k word-write to flexram execution time: 8 kb eeprom backup 16 kb eeprom backup 32 kb eeprom backup 340 385 475 1700 1800 2000 ?s ?s ?s longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 360 540 ?s t eewr32b8k t eewr32b16k t eewr32b32k longword-write to flexram execution time: 8 kb eeprom backup 16 kb eeprom backup 32 kb eeprom backup 545 630 810 1950 2050 2250 ?s ?s ?s 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 6.4.1.3 flash current and power specfications table 20. flash current and power specfications symbol description typ. unit i dd_pgm worst case programming current in program flash 10 ma 6.4.1.4 reliability specifications table 21. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 21. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree8k write endurance eeprom backup to flexram ratio = 16 eeprom backup to flexram ratio = 128 eeprom backup to flexram ratio = 512 eeprom backup to flexram ratio = 4096 eeprom backup to flexram ratio = 8192 35 k 315 k 1.27 m 10 m 20 m 175 k 1.6 m 6.4 m 50 m 100 m writes writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c ? t j ? 125c. 3. write endurance represents the number of writes to each flexram location at -40c ?tj ? 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup per subsystem. minimum and typical values assume all byte-writes to flexram. 6.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. the bytes not assigned to data flash via the flexnvm partition code are used by the ftfl to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = write_efficiency n eeprom ? 2 eeesplit eeesize eeesplit eeesize nvmcycd where peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 34 freescale semiconductor, inc.
? writes_subsystem ? minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) ? eeprom ? allocated flexnvm for each eeprom subsystem based on depart; entered with program partition command ? eeesplit ? flexram split factor for subsystem; entered with the program partition command ? eeesize ? allocated flexram based on depart; entered with program partition command ? write_efficiency ? ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycd ? data flash cycling endurance figure 10. eeprom backup writes to flexram peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 35
6.4.2 ezport switching specifications table 22. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 16 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 11. ezport timing diagram 6.5 security and integrity modules there are no specifications necessary for the devices security and integrity modules. peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 36 freescale semiconductor, inc.
6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 23 and table 24 are achievable on the differential pins adcx_dp0, adcx_dm0. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 25 and table 26 . all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 23. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 23. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes c rate adc conversion rate ? 13 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 5 c rate adc conversion rate 16 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 5 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 ? analog source resistance. the r as / c as time constant should be kept to <1ns. 4. to use the maximum adc conversion clock frequency, the adhsc bit should be set and the adlpc bit should be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin input pin input pin input pin input pin
6.6.1.2 16-bit adc electrical characteristics table 24. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source adlpc=1, adhsc=0 adlpc=1, adhsc=1 adlpc=0, adhsc=0 adlpc=0, adhsc=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error 12 bit modes <12 bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity 12 bit modes <12 bit modes 0.7 0.2 -1.1 to +1.9 -0.3 to 0.5 lsb 4 5 inl integral non- linearity 12 bit modes <12 bit modes 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 e fs full-scale error 12 bit modes <12 bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error 16 bit modes ?13 bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16 bit differential mode avg=32 avg=4 16 bit single-ended mode avg=32 avg=4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit differential mode avg=32 16 bit single-ended mode avg=32 ?94 -85 db db 7 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 24. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes sfdr spurious free dynamic range 16 bit differential mode avg=32 16 bit single-ended mode avg=32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope ?40c to 105c 1.715 mv/c v temp25 temp sensor voltage 25c 719 mv 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock <16mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock <12mhz. 7. input data is 1 khz sine wave. adc conversion clock <12mhz. peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 40 freescale semiconductor, inc.
figure 13. typical enob vs. adc_clk for 16-bit differential mode figure 14. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 41
6.6.1.3 16-bit adc with pga operating conditions table 25. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2 , 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k? in+ to in- 4 r as analog source resistance 100 ? 5 t s adc sampling time 1.25 s 6 c rate adc conversion rate ? 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 37.037 250 ksps 8 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 42 freescale semiconductor, inc.
6.6.1.4 16-bit adc with pga characteristics with chop enabled (adc_pga[pgachpb] =0) table 26. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 644 ?a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 ?a gain =64, v refpga =1.2v, v cm =0.1v 0.57 ?a g gain 4 pgag=0 pgag=1 pgag=2 pgag=3 pgag=4 pgag=5 pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 26. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes e il input leakage error all modes i in r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) v pp,diff maximum differential input signal swing where v x = v refpga 0.583 v 6 snr signal-to-noise ratio gain=1 gain=64 80 52 90 66 db db 16-bit differential mode, average=32 thd total harmonic distortion gain=1 gain=64 85 49 100 95 db db 16-bit differential mode, average=32, f in =100hz sfdr spurious free dynamic range gain=1 gain=64 85 53 105 88 db db 16-bit differential mode, average=32, f in =100hz enob effective number of bits gain=1, average=4 gain=64, average=4 gain=1, average=32 gain=2, average=32 gain=4, average=32 gain=8, average=32 gain=16, average=32 gain=32, average=32 gain=64, average=32 11.6 7.2 12.8 11.0 7.9 7.3 6.8 6.8 7.5 13.4 9.6 14.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits bits bits bits 16-bit differential mode,f in =100h z sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. 6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 44 freescale semiconductor, inc.
6.6.2 cmp and 6-bit dac electrical specifications table 27. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 ?a i ddls supply current, low-speed mode (en=1, pmode=0) 20 ?a v ain analog input voltage v ss ? 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 cr0[hystctr] = 00 cr0[hystctr] = 01 cr0[hystctr] = 10 cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd ? 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 ?s i dac6b 6-bit dac current adder (enabled) 7 ?a inl 6-bit dac integral non-linearity ?0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity ?0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 45
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 15. typical hysteresis vs. vin level (vdd=3.3v, pmode=0) peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 46 freescale semiconductor, inc.
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 16. typical hysteresis vs. vin level (vdd=3.3v, pmode=1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 28. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 t a temperature 40 105 c c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be vdda or the voltage output of the vref module (vref_out) 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 47
6.6.3.2 12-bit dac operating behaviors table 29. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 ?a i dda_dac hp supply current high-speed mode 700 ?a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 ?s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 ?s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 ?s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr 100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda > = 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 ?v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance load = 3 k? 250 ? sr slew rate -80h
6. vdda = 3.0v, reference select set for vdda (dacx_co:dacrfs = 1), high power mode(dacx_c0:lpen = 0), dac set to 0x800, temp range from -40c to 105c figure 17. typical inl error vs. digital code peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 49
figure 18. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 30. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature 40 105 c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 50 freescale semiconductor, inc.
table 31. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v v out voltage reference output factory trim 1.1584 1.2376 v v out voltage reference output user trim 1.193 1.197 v v step voltage reference trim step 0.5 mv v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv i bg bandgap only current 80 a 1 i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1
6.7 timers see general switching specifications . 6.8 communication interfaces 6.8.1 can switching specifications see general switching specifications . 6.8.2 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 35. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 25 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dsisc delay (t bs x ) ns ds dsisc to dsics n invalid delay (t bs x ) ns ds dsisc to dsist valid . ns ds dsisc to dsist invalid ns ds dsisin to dsisc input setup ns ds dsisc to dsisin input hold ns . the delay is programmable in sixctarnssc and sixctarncssc. . the delay is programmable in sixctarnasc and sixctarnasc. eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 19. dspi classic spi timing master mode table 36. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 12.5 mhz ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 10 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 20. dspi classic spi timing slave mode peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 53
6.8.3 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 37. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 12.5 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dsisc delay (t bs x ) ns ds dsisc to dsics n invalid delay (t bs x ) ns ds dsisc to dsist valid ns ds dsisc to dsist invalid -. ns ds dsisin to dsisc input setup . ns ds dsisc to dsisin input hold ns . the dsi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum freuency of operation is reduced. . the delay is programmable in sixctarnssc and sixctarncssc. . the delay is programmable in sixctarnasc and sixctarnasc. ds ds ds ds ds ds first data last data ds first data data last data ds data dsicsn dsisc (cl) dsisin dsist figure . dsi classic si timing master mode eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 38. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 6.25 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 19 ns ds16 dspi_ss inactive to dspi_sout not driven 19 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 22. dspi classic spi timing slave mode 6.8.4 i 2 c switching specifications see general switching specifications . 6.8.5 uart switching specifications see general switching specifications . peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 55
6.8.6 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 6.8.6.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 39. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1.0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 20.5 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 56 freescale semiconductor, inc.
s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 23. i2s/sai timing master modes table 40. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 5.8 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 20.6 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 5.8 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 57
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 24. i2s/sai timing slave modes 6.8.6.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 41. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 53 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. 58 freescale semiconductor, inc.
s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 25. i2s/sai timing master modes table 42. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 7.6 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 67 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 6.5 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 59
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 26. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 43. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 8 15 mhz 2 , 3 f elemax electrode oscillator frequency 1 1.8 mhz 2 , 4 c ref internal reference capacitor 1 pf v delta oscillator delta voltage 500 mv 2 , 5 i ref reference oscillator current source base current 2 32 2 32 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 43. tsi electrical specifications (continued) symbol description min. typ. max. unit notes t con20 response time @ 20 pf 8 15 25 ?s 12 i tsi_run current added in run mode 55 ?a i tsi_lp low power mode current adder 1.3 2.5 ?a 13 1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. fixed external capacitance of 20 pf. 3. refchrg = 2, extchrg=0. 4. refchrg = 0, extchrg = 10. 5. v dd = 3.0 v. 6. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 7. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 8. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 10. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 11. sensitivity defines the minimum capacitance change when a single count from the tsi module changes, it is equal to (c ref * i ext )/( i ref * ps * nscn). sensitivity depends on the configuration used. the typical value listed is based on the following configuration: iext = 6 ?a (extchrg = 2), ps = 128, nscn = 2, i ref = 16 = 2 = 32 table continues on the next page... eripheral operating reuirements and behaviors sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 44. lcd electricals (continued) symbol description min. typ. max. unit notes v ireg ripple hrefsel = 0 hrefsel = 1 30 50 mv mv i vireg v ireg current adder rven = 1 1 a 4 i rbias rbias current adder ladj = 10 or 11 high load (lcd glass capacitance ? 8000 pf) ladj = 00 or 01 low load (lcd glass capacitance ? 2000 pf) 10 1 a a r rbias rbias resistor values ladj = 10 or 11 high load (lcd glass capacitance ? 8000 pf) ladj = 00 or 01 low load (lcd glass capacitance ? 2000 pf) 0.28 2.98 m? m? vll2 vll2 voltage hrefsel = 0 hrefsel = 1 2.0 5% 3.3 5% 2.0 3.3 v v vll3 vll3 voltage hrefsel = 0 hrefsel = 1 3.0 5% 5 5% 3.0 5 v v 1. the actual value used could vary with tolerance. 2. for highest glass capacitance values, lcd_gcr[ladj] should be configured as specified in the lcd controller chapter within the device?s reference manual. 3. v ireg maximum should never be externally driven to any level other than v dd - 0.15 v 4. 2000 pf load lcd, 32 hz frame frequency 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawing?s document number: dimensions k30 sub-family data sheet, rev. 2, 4/2012. 62 freescale semiconductor, inc.
if you want the drawing for this package then use this document number 80-pin lqfp 98ass23174w 81-pin mapbga 98asa00344d 8 pinout 8.1 k30 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 81 map bga 80 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport e4 1 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx i2c1_sda rtc_clkout e3 2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx i2c1_scl spi1_sin e2 3 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts_ b f4 4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts_ b spi1_sout e7 vdd vdd vdd f7 vss vss vss h7 5 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx g4 6 pte5 disabled pte5 spi1_pcs2 uart3_rx e6 7 vdd vdd vdd g7 8 vss vss vss f1 9 pte16 adc0_se4a adc0_se4a pte16 spi0_pcs0 uart2_tx ftm_clkin0 ftm0_flt3 f2 10 pte17 adc0_se5a adc0_se5a pte17 spi0_sck uart2_rx ftm_clkin1 lptmr0_ alt3 g1 11 pte18 adc0_se6a adc0_se6a pte18 spi0_sout uart2_cts_ b i2c0_sda g2 12 pte19 adc0_se7a adc0_se7a pte19 spi0_sin uart2_rts_ b i2c0_scl l6 vss vss vss k1 13 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 k2 14 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pinout k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 63
81 map bga 80 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport l1 15 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 l2 16 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 f5 17 vdda vdda vdda g5 18 vrefh vrefh vrefh g6 19 vrefl vrefl vrefl f6 20 vssa vssa vssa l3 21 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 k5 22 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 l7 rtc_ wakeup_b rtc_ wakeup_b rtc_ wakeup_b l4 23 xtal32 xtal32 xtal32 l5 24 extal32 extal32 extal32 k6 25 vbat vbat vbat j6 26 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts_ b/ uart0_col_ b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk h8 27 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di j7 28 pta2 jtag_tdo/ trace_swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do h9 29 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts_ b ftm0_ch0 jtag_tms/ swd_dio j8 30 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b k7 31 pta5 disabled pta5 ftm0_ch2 cmp2_out i2s0_tx_ bclk jtag_trst_ b e5 vdd vdd vdd g3 vss vss vss k8 32 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 i2s0_txd0 ftm1_qd_ pha l8 33 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 i2s0_tx_fs ftm1_qd_ phb k9 34 pta14 disabled pta14 spi0_pcs0 uart0_tx i2s0_rx_ bclk i2s0_txd1 l9 35 pta15 disabled pta15 spi0_sck uart0_rx i2s0_rxd0 pinout k30 sub-family data sheet, rev. 2, 4/2012. 64 freescale semiconductor, inc.
81 map bga 80 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport j10 36 pta16 disabled pta16 spi0_sout uart0_cts_ b/ uart0_col_ b i2s0_rx_fs i2s0_rxd1 h10 37 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts_ b i2s0_mclk l10 38 vdd vdd vdd k10 39 vss vss vss l11 40 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 k11 41 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_ alt1 j11 42 reset_b reset_b reset_b g11 43 ptb0/ llwu_p5 lcd_p0/ adc0_se8/ adc1_se8/ tsi0_ch0 lcd_p0/ adc0_se8/ adc1_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_ pha lcd_p0 g10 44 ptb1 lcd_p1/ adc0_se9/ adc1_se9/ tsi0_ch6 lcd_p1/ adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_ phb lcd_p1 g9 45 ptb2 lcd_p2/ adc0_se12/ tsi0_ch7 lcd_p2/ adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts_ b ftm0_flt3 lcd_p2 g8 46 ptb3 lcd_p3/ adc0_se13/ tsi0_ch8 lcd_p3/ adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts_ b/ uart0_col_ b ftm0_flt0 lcd_p3 d11 47 ptb8 lcd_p8 lcd_p8 ptb8 uart3_rts_ b lcd_p8 e10 48 ptb9 lcd_p9 lcd_p9 ptb9 spi1_pcs1 uart3_cts_ b lcd_p9 d10 49 ptb10 lcd_p10/ adc1_se14 lcd_p10/ adc1_se14 ptb10 spi1_pcs0 uart3_rx ftm0_flt1 lcd_p10 c10 50 ptb11 lcd_p11/ adc1_se15 lcd_p11/ adc1_se15 ptb11 spi1_sck uart3_tx ftm0_flt2 lcd_p11 b10 51 ptb16 lcd_p12/ tsi0_ch9 lcd_p12/ tsi0_ch9 ptb16 spi1_sout uart0_rx ewm_in lcd_p12 e9 52 ptb17 lcd_p13/ tsi0_ch10 lcd_p13/ tsi0_ch10 ptb17 spi1_sin uart0_tx ewm_out_b lcd_p13 d9 53 ptb18 lcd_p14/ tsi0_ch11 lcd_p14/ tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_ bclk ftm2_qd_ pha lcd_p14 c9 54 ptb19 lcd_p15/ tsi0_ch12 lcd_p15/ tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs ftm2_qd_ phb lcd_p15 b9 55 ptc0 lcd_p20/ adc0_se14/ tsi0_ch13 lcd_p20/ adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extrg i2s0_txd1 lcd_p20 pinout k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 65
81 map bga 80 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport d8 56 ptc1/ llwu_p6 lcd_p21/ adc0_se15/ tsi0_ch14 lcd_p21/ adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_ b ftm0_ch0 i2s0_txd0 lcd_p21 c8 57 ptc2 lcd_p22/ adc0_se4b/ cmp1_in0/ tsi0_ch15 lcd_p22/ adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts_ b ftm0_ch1 i2s0_tx_fs lcd_p22 b8 58 ptc3/ llwu_p7 lcd_p23/ cmp1_in1 lcd_p23/ cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_ bclk lcd_p23 59 vss vss vss a11 60 vll3 vll3 vll3 a10 61 vll2 vll2 vll2 a9 62 vll1 vll1 vll1 b11 63 vcap2 vcap2 vcap2 c11 64 vcap1 vcap1 vcap1 a8 65 ptc4/ llwu_p8 lcd_p24 lcd_p24 ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 cmp1_out lcd_p24 d7 66 ptc5/ llwu_p9 lcd_p25 lcd_p25 ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 cmp0_out lcd_p25 c7 67 ptc6/ llwu_p10 lcd_p26/ cmp0_in0 lcd_p26/ cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extrg i2s0_rx_ bclk i2s0_mclk lcd_p26 b7 68 ptc7 lcd_p27/ cmp0_in1 lcd_p27/ cmp0_in1 ptc7 spi0_sin i2s0_rx_fs lcd_p27 a7 69 ptc8 lcd_p28/ adc1_se4b/ cmp0_in2 lcd_p28/ adc1_se4b/ cmp0_in2 ptc8 i2s0_mclk lcd_p28 d6 70 ptc9 lcd_p29/ adc1_se5b/ cmp0_in3 lcd_p29/ adc1_se5b/ cmp0_in3 ptc9 i2s0_rx_ bclk ftm2_flt0 lcd_p29 c6 71 ptc10 lcd_p30/ adc1_se6b lcd_p30/ adc1_se6b ptc10 i2c1_scl i2s0_rx_fs lcd_p30 c5 72 ptc11/ llwu_p11 lcd_p31/ adc1_se7b lcd_p31/ adc1_se7b ptc11/ llwu_p11 i2c1_sda i2s0_rxd1 lcd_p31 d4 73 ptd0/ llwu_p12 lcd_p40 lcd_p40 ptd0/ llwu_p12 spi0_pcs0 uart2_rts_ b lcd_p40 d3 74 ptd1 lcd_p41/ adc0_se5b lcd_p41/ adc0_se5b ptd1 spi0_sck uart2_cts_ b lcd_p41 c3 75 ptd2/ llwu_p13 lcd_p42 lcd_p42 ptd2/ llwu_p13 spi0_sout uart2_rx lcd_p42 b3 76 ptd3 lcd_p43 lcd_p43 ptd3 spi0_sin uart2_tx lcd_p43 a3 77 ptd4/ llwu_p14 lcd_p44 lcd_p44 ptd4/ llwu_p14 spi0_pcs1 uart0_rts_ b ftm0_ch4 ewm_in lcd_p44 a2 78 ptd5 lcd_p45/ adc0_se6b lcd_p45/ adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b/ uart0_col_ b ftm0_ch5 ewm_out_b lcd_p45 pinout k30 sub-family data sheet, rev. 2, 4/2012. 66 freescale semiconductor, inc.
81 map bga 80 lqfp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport b2 79 ptd6/ llwu_p15 lcd_p46/ adc0_se7b lcd_p46/ adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 ftm0_flt0 lcd_p46 a1 80 ptd7 lcd_p47 lcd_p47 ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 lcd_p47 k3 nc nc nc h4 nc nc nc f3 nc nc nc h1 nc nc nc h2 nc nc nc j1 nc nc nc j2 nc nc nc j3 nc nc nc h3 nc nc nc k4 nc nc nc h5 nc nc nc j5 nc nc nc h6 nc nc nc j9 nc nc nc j4 nc nc nc h11 nc nc nc f11 nc nc nc e11 nc nc nc f10 nc nc nc f9 nc nc nc f8 nc nc nc e8 nc nc nc b6 nc nc nc a6 nc nc nc a5 nc nc nc b5 nc nc nc d5 nc nc nc c4 nc nc nc b4 nc nc nc a4 nc nc nc b1 nc nc nc c2 nc nc nc c1 nc nc nc d2 nc nc nc d1 nc nc nc e1 nc nc nc pinout k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 67
8.2 k30 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout k30 sub-family data sheet, rev. 2, 4/2012. 68 freescale semiconductor, inc.
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vssa vrefl vrefh vdda pga1_dm/adc1_dm0/adc0_dm3 pga1_dp/adc1_dp0/adc0_dp3 pga0_dm/adc0_dm0/adc1_dm3 pga0_dp/adc0_dp0/adc1_dp3 pte19 pte18 pte17 pte16 vss vdd pte5 pte4/llwu_p2 pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ptd7 ptd6/llwu_p15 ptd5 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc11/llwu_p11 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 vcap1 vcap2 vll1 vll2 vll3 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb19 ptb18 ptb17 ptb16 ptb11 ptb10 ptb9 ptb8 ptb3 ptb2 ptb1 ptb0/llwu_p5 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 vbat extal32 xtal32 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 figure 27. k30 80 lqfp pinout diagram pinout k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 69
1 a ptd7 b nc c nc d nc e nc f pte16 g pte18 h nc j nc k pga0_dp/ 1 l pga1_dp/ 2 ptd5 ptd6/ nc nc pte2/ pte17 pte19 nc nc pga0_dm/ 2 pga1_dm/ 3 ptd4/ ptd3 ptd2/ ptd1 pte1/ nc vss nc nc nc 3 vref_out/ 4 nc nc nc ptd0/ pte0 pte3 pte5 nc nc nc 4 xtal32 5 nc nc ptc11/ nc vdd vdda vrefh nc nc dac0_out/ 5 extal32 6 nc nc ptc10 ptc9 vdd vssa vrefl nc pta0 vbat 6 vss 7 ptc8 ptc7 ptc6/ ptc5/ vdd vss vss pte4/ pta2 pta5 7 rtc_ 8 ptc4/ ptc3/ ptc2 ptc1/ nc nc ptb3 pta1 pta4/ pta12 8 pta13/ 9 vll1 ptc0 ptb19 ptb18 ptb17 nc ptb2 pta3 nc pta14 9 pta15 10 vll2 ptb16 ptb11 ptb10 ptb9 nc ptb1 pta17 pta16 vss 10 vdd 11 a vll3 b vcap2 c vcap1 d ptb8 e nc f nc g ptb0/ h nc j reset_b k pta19 11 l pta18 llwu_p14 llwu_p8 llwu_p15 llwu_p7 llwu_p13 llwu_p11 llwu_p10 llwu_p12 llwu_p9 llwu_p6 llwu_p1 llwu_p0 llwu_p5 llwu_p2 llwu_p3 cmp1_in3/ adc0_se23 adc0_dm0/ adc1_dm3 adc0_dp0/ adc1_dp3 cmp1_in5/ cmp0_in5/ adc1_se18 adc1_dm0/ adc0_dm3 adc1_dp0/ adc0_dp3 wakeup_b llwu_p4 figure 28. k30 81 mapbga pinout diagram 9 revision history the following table provides a revision history for this document. table 45. revision history rev. no. date substantial changes 1 3/2012 initial public release table continues on the next page... revision history sub-family data sheet, rev. , /. freescale semiconductor, inc.
table 45. revision history (continued) rev. no. date substantial changes 2 4/2012 replaced tbds throughout. updated "power consumption operating behaviors" table. updated "adc electrical specifications" section. updated "vref full-range operating behaviors" table. updated "i2s/sai switching specifications" section. updated "tsi electrical specifications" table. revision history k30 sub-family data sheet, rev. 2, 4/2012. freescale semiconductor, inc. 71
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